Palindrome Detector
“Evaluating computational symmetry in real-time hardware through Karnaugh map minimization and zero instruction latency.”
A physical 4-bit combinational logic circuit wired on breadboard with 74LS TTL ICs that evaluates bit symmetry with zero clock cycles.
- Role
- Logic Circuit Designer
- Context
- 1 Week (DLD Lab @ UET Taxila)
- Team
- Solo Project
- Core Stack
- TTL 74LS86 (XOR), 74LS04 (NOT), 74LS08 (AND), Breadboard
Fig 1.0 — Architecture execution snapshot (Palindrome Detector)
The Friction
Why build a palindrome evaluator in hardware instead of a 3-line software loop?
In software, checking whether a word or bit sequence is a palindrome is a trivial two-pointer loop: compare the first and last elements, then step inwards. But a CPU running that loop requires hundreds of clock cycles, fetching instructions from cache, updating registers, and branching.
In Digital Logic Design, the question is inverted: can we evaluate symmetry instantaneously without a CPU, without a clock, and without a sequence of instructions? By analyzing the Boolean truth table of a 4-bit word, we can detect symmetry at the speed of light—governed solely by the physical propagation delay of electrons passing through silicon gates.
Deliberate Constraints
The system architecture was not chosen in an unconstrained vacuum. Each structural decision emerged directly from four non-negotiable technical boundaries.
No sequential clock signals, flip-flops, or time-step iteration.
The evaluation must be purely combinational: output changes instantaneously upon input transition within gate propagation latency (< 25ns).
Breadboard area and physical IC pin counts are strictly constrained.
Used Karnaugh map minimization to reduce raw 16-row Boolean truth tables down to minimal equivalence equations.
74LS TTL integrated circuits require strict voltage boundaries (0.8V LOW, 2.0V HIGH).
Required active pull-down resistor networks on DIP switch inputs to avoid floating indeterminate logic states.
No microcontrollers, no VHDL simulation abstractions; physical silicon breadboarding only.
Hand-wired circuit connections with color-coded signal routing and visual LED state output.
System Architecture & Data Pipeline
The circuit evaluates a 4-bit binary input word (A, B, C, D). A 4-bit word is symmetric (a palindrome) if and only if bit A matches bit D, and bit B matches bit C. The Boolean logic reduces directly to the conjunction of two XNOR gates: Y = (A ⊙ D) · (B ⊙ C).
Alto, Cultus, Corolla. Standard tiered rental base.
Audi A6, BMW 7, Land Cruiser. Chauffeur insurance rate.
Sportage, Tucson, Fortuner. All-terrain security deposit.
Bolan, Hiace, Coaster. High-capacity commercial rate.
Dynamic Polymorphism at Runtime: The orchestrator holds a single container std::vector<Vehicle*> fleet. When executing reservations or computing quotes, method calls to v->calculateCost(days) dynamically dispatch to the concrete subclass implementation through each instance's vtable pointer.
Subsystem Decomposition
4-Bit Binary Input Stage
DIP Switch & Pull-Down ResistorsProvides clean digital binary logic levels (0000 through 1111) without floating inputs.
Outer Bit Equivalence Stage
74LS86 XOR + 74LS04 Inverter (XNOR)Compares Most Significant Bit (A) and Least Significant Bit (D) for equivalence.
Inner Bit Equivalence Stage
74LS86 XOR + 74LS04 Inverter (XNOR)Compares middle bits (B and C) for equivalence.
Conjunction & Indicator Stage
74LS08 AND Gate & High-Efficiency LEDCombines outer and inner equivalence signals to illuminate indicator only when symmetry holds.
The Hard Part: Floating Inputs & Gate Propagation Glitches
How high-impedance floating pins produce erratic truth states on unclocked breadboards.
During initial assembly, the palindrome indicator LED flickered randomly whenever the designer's hand moved near the breadboard, and certain symmetrical combinations failed to illuminate the output.
TTL logic inputs (74LS series) are not standard voltage meters; they are current-sinking bipolar junction transistors. Leaving an input pin disconnected or switching a floating contact does not produce a logic 0—it floats in a high-impedance intermediate region (1.2V–1.6V) that causes internal transistors to oscillate rapidly.
/* 4-Bit Palindrome Truth Table (16 States) */
Symmetric Palindromes (6 total):
0000, 0110, 1001, 1111 (plus duplicate parity checks)
Truth Table Reduction:
Y = A'B'C'D' + A'BC C'D' + ...
Applying Boolean Algebra / K-Map Minimization:
Y = (A'D' + AD) · (B'C' + BC)
Y = (A ⊙ D) · (B ⊙ C)
/* Gate Propagation Delay */
74LS86 (XOR): 10ns
74LS04 (NOT): 6ns
74LS08 (AND): 8ns
Total Circuit Latency: 24ns (< 0.000000024 seconds)We installed a precision 10kΩ pull-down resistor array on all four input switches to sink floating currents to ground, and placed bypass capacitors between the VCC and GND pins of each IC to eliminate power rail switching noise.
In digital theory, a wire is an ideal mathematical line. In physical engineering, a wire is an antenna, an inductor, and a capacitor. Respecting physical signal grounding is the first rule of computing.
Hardware Truth Table Verification
Full 16-state input vector test verifying zero false-positives and sub-30ns propagation latency.
Engineering Reflection
“Software programs simulate logic; hardware combinational circuits ARE logic.”
In modern programming, we rarely contemplate what happens to a bit between the time it is read and the time it produces an answer. We expect the operating system and CPU to handle instruction scheduling.
Building this circuit taught me that computation can happen without a program. There is no instruction pointer, no register allocation, and no memory address. Electrons simply propagate through gate channels, settling into truth states in twenty billionths of a second.
Understanding digital logic at the silicon level demystifies the entire computing stack.
Interested in discussing this architecture?
I'm always open to technical dialogue, code reviews, and exploring system constraints.